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<h1> Evan Speight </A> <!WA0><A HREF="http://www-ce.rice.edu/cgi-bin/finger?espeight">(espeight@ece.rice.edu)</A> </h1> 
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Colors too washed out with the background picture?  Click <!WA2><a href="http://www-ece.rice.edu/~espeight/nobackground.html"> <blink> here </blink> </a>.
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Graduate Research Assistant<br>
Department of Electrical and Computer Engineering<br>
Rice University<br>
P.O. Box 1892<br>
Houston, TX 77251-1892
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<b>Advisor:</b> <!WA3><a href="http://www-ce.rice.edu/ce/members/jkb/htdocs/jkb.html"> John K. Bennett </a>
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<h2><!WA4><img width=34 height=37 align=middle src="http://www-ece.rice.edu/~espeight/icons/bighand.right.gif">   Research Interests:</h2>
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<!WA5><img alt="o" src="http://www-ece.rice.edu/~espeight/icons/red.gif"> Adaptive performance tuning of shared-memory multiprocessors<br>
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<!WA6><img alt="o" src="http://www-ece.rice.edu/~espeight/icons/red.gif"> Parallel program performance visualization<br>
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<!WA7><img alt="o" src="http://www-ece.rice.edu/~espeight/icons/red.gif"> Shared-memory parallel computer design<br>
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<h2><!WA8><img width=34 height=37 align=middle src="http://www-ece.rice.edu/~espeight/icons/bighand.right.gif">  Dissertation Research:</h2>
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<!WA9><img alt="o" src="http://www-ece.rice.edu/~espeight/icons/red.gif"><!WA10><A HREF="http://www-ece.rice.edu/~espeight/proposal.html"> Adaptive Performance Tuning for Software DSM Systems</A><br>
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<h2><!WA11><img width=34 height=37 align=middle src="http://www-ece.rice.edu/~espeight/icons/bighand.right.gif">  Education:</h2>
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<!WA12><img alt="o" src="http://www-ece.rice.edu/~espeight/icons/red.gif"> M.S. <!WA13><a href="http://www.rice.edu"> <!WA14><img WIDTH=40 height=45 align=middle src="http://www-ece.rice.edu/~espeight/icons/rice_shield.gif"> Rice University </a>, 1993.<br>
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<!WA15><img alt="o" src="http://www-ece.rice.edu/~espeight/icons/red.gif"> B.S. <!WA16><a href="http://www.stanford.edu"> <!WA17><img WIDTH=40 height=45 align=middle src="http://www-ece.rice.edu/~espeight/icons/logo.www.gif">Stanford University</a>, 1991.<br>
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<h2><!WA18><img width=34 height=37 align=middle src="http://www-ece.rice.edu/~espeight/icons/bighand.right.gif">  Publications </h2>
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<!WA19><img alt="o" src="http://www-ece.rice.edu/~espeight/icons/blue.gif"> <!WA20><A HREF="http://www-ece.rice.edu/~espeight/publications.html"> All in one list</a> 
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<h3> By topic </h3>
<!WA21><img alt="o" src="http://www-ece.rice.edu/~espeight/icons/red.gif"> <!WA22><A HREF="http://www-ece.rice.edu/~espeight/performance_deb.html"> Performance Debugging </a> <br>
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<!WA23><img alt="o" src="http://www-ece.rice.edu/~espeight/icons/red.gif"> <!WA24><A HREF="http://www-ece.rice.edu/~espeight/network_cache.html"> Shared Remote Data Caching</a> <br>
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<!WA25><img alt="o" src="http://www-ece.rice.edu/~espeight/icons/red.gif"> <!WA26><A HREF="http://www-ece.rice.edu/~espeight/sm-multi.html"> Shared-Memory Multiprocessors </a> <br>
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<h2><!WA27><img width=34 height=37 align=middle src="http://www-ece.rice.edu/~espeight/icons/bighand.right.gif"><!WA28><A HREF="http://www-ece.rice.edu/~espeight/cv.ps"> Resume</A></h2> 
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<H3>Computer Architecture Related Pages</H3>

<P>The
<!WA29><A HREF="http://www.cs.wisc.edu/~arch/www">
World Wide Web Computer Architecture Page</A>
at the University of Wisconsin.

<P>The
<!WA30><A HREF="http://www-flash.stanford.edu/">FLASH</A>
project is a shared memory multiprocessor,
a follow on to the DASH project.  The Flash home page also
has many architecture related pointers.

<P>There is a table describing the performance of various machines at
<!WA31><A HREF="http://performance.netlib.org/performance/html/spec.html">
netlib SPECmarks</A>.
For integer uniprocessor performance, look at items labeled
"<em>CINT92 Summary</em>", and for floating point uniprocessor performance,
look at items labeled "<em>CFP92 Summary</em>".

<P>The Computer Architecture Group at MIT has a home page,
<!WA32><A HREF="http://cag-www.lcs.mit.edu/">CAG</A>.  They have
some dataflow machine projects there, such as the <em>J-machine</em>, the
<em>M-machine</em>, and <em>Alewife</em> (arguably).  There is also some work
on FPGA's called <em>Virtual Wires</em>.

<P>Carver Mead at Caltech has a group called the
<!WA33><A HREF="http://carver.pcmp.caltech.edu/">Physics of Computation</A>.
They are working on "making chips to emulate functions of the nervous
system, like retinas and cochleas".  There is a set of design tools
available there called the <em>Chipmunk design tools</em>.

<P>The Data Diffusion Machine,
<!WA34><A HREF="http://www.pact.srf.ac.uk/DDM">DDM</A>,
at the University of Bristol is a virtual shared memory
multiprocessor.  The technique used goes by the acronym
<em>COMA</em> (Cache Only Memory Architecture).  Also their
home page has a pointer to a list of related research projects
which is great.

<P>The Wisconsin Wind Tunnel project,
<!WA35><A HREF="http://www.cs.wisc.edu/~wwt">WWT</A>,
is working on a new interface for
parallel computation called <em>Tempest</em>, which is being
implementing on a CM-5.

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<!WA36><a  href=mailto:espeight@rice.edu><!WA37><IMG  WIDTH=34 HEIGHT=37 SRC="http://www-ece.rice.edu/~espeight/icons/mailbutton.gif" align=middle> espeight@rice.edu</a>

<h4> You were the <!WA38><img src="http://riceinfo.rice.edu/cgi-bin/counter.xbm?http://www-ce.rice.edu/ce/members/espeight/htdocs/espeight.html" align="top"> th person to visit this page since December 18, 1995

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  <dt> <!WA39><a href="http://www-ece.rice.edu/">
       <!WA40><img alt="[Rice ECE Home Page]" SRC="http://www-ece.rice.edu/~espeight/icons/back_home.gif"> Rice ECE
Department </a>

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<address>Evan Speight (espeight@ece.rice.edu) </address>

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